Stochastic Process Variation in Deep-Submicron CMOS by Amir Zjajo

Author:Amir Zjajo
Language: eng
Format: epub
Publisher: Springer Netherlands, Dordrecht

4.1 Thermal Model

A 3D integrated circuit contains multiple vertically stacked silicon layers, each containing processing elements and memory modules (Fig. 4.1) [22, 23]. An off-line temperature profile estimation methodology [21] has the capability to include layout geometry of individual circuit blocks in a chip (Fig. 4.2).

Fig. 4.13D chip package with processing elements (PE) on vertically stacked silicon layers [22, 23]

Fig. 4.2Off-line setup of the methodology for thermal profile estimation [21]

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